MT-085 tutorial fundamentals of direct digital synthesis (dds) fundamental dds architecture with the widespread use of digital techniques in instrumentation and communications systems, a digitally-controlled method of generating multiple frequencies from a reference frequency source has evolved called direct digital synthesis (dds). the basic arch itecture is shown in figure 1. in this simplified model, a stable clock dr ives a programmable-read-only-memory (prom) which stores one or more integral number of cy cles of a sinewave (or other arbitrary waveform, for that matter). as the address counter st eps through each memory location, the corresponding digital amplitude of the signal at each location dr ives a dac which in turn generates the analog output signal. the spectral purity of the final an alog output signal is determined primarily by the dac. the phase noise is basically that of the reference clock. because a dds system is a sampled data system, all the issues involved in sampling must be considered: quantization noise, alia sing, filtering, etc. fo r instance, the higher order harmonics of the dac output frequencies fold back into th e nyquist bandwidth, making them unfilterable, whereas, the higher order harmonics of the output of pll-based synthesizers can be filtered. there are other considerations which will be discussed shortly. f c address counter sin lookup table n-bits clock register lpf dac f out lookup table contains sine data for integral number of cycles n-bits f c address counter sin lookup table n-bits clock register lpf dac f out lookup table contains sine data for integral number of cycles n-bits figure 1 : fundamental direct digital synthesis system rev.0, 10/08, wk page 1 of 9
MT-085 a fundamental problem with this simple dds syst em is that the final output frequency can be changed only by changing the reference clock frequency or by reprogramming the prom, making it rather inflexible. a practical dds system implements this basic function in a much more flexible and efficient manner using digi tal hardware called a numerically controlled oscillator (nco). a block diagram of such a system is shown in figure 2. f c serial or byte load register n n frequency control phase register lpf dac parallel delta phase register m clock n n phase accumulator n phase truncation 12-19 bits amplitude truncation 2 n = f o m ? f c n-bits n = 24 - 48 bits phase-to amplitude converter m = tuning word system clock (10-14) figure 2: a flexibl e dds system the heart of the system is the phase accumulator whose contents is updated once each clock cycle. each time the phase accumulator is upd ated, the digital number, m, stored in the delta phase register is added to the number in the phase accu mulator register. assume that the number in the delta phase register is 00...01 and that th e initial contents of th e phase accumulator is 00...00. the phase accumulator is u pdated by 00...01 on each clock cycl e. if the accumulator is 32-bits wide, 2 32 clock cycles (over 4 billi on) are required before th e phase accumulator returns to 00...00, and the cycle repeats. the truncated output of the phase accumulator serv es as the address to a sine (or cosine) lookup table. each address in the lookup table corresponds to a phase point on the sinewave from 0 to 360. the lookup table contains the correspondi ng digital amplitude information for one complete cycle of a sinewave. (actually, only da ta for 90 is required because the quadrature data is contained in the two ms bs). the lookup table therefore ma ps the phase information from the phase accumulator into a digital amplitude word, which in turn drives the dac. this is shown graphically using the "phase wheel" in figure 3. page 2 of 9
MT-085 consider the case for n = 32, and m = 1. the phase accumulator steps through each of 2 32 possible outputs before it overflows and restar ts. the corresponding output sinewave frequency is equal to the input cloc k frequency divided by 2 32 . if m=2, then the phase accumulator register "rolls over" twice as fast, and the output freq uency is doubled. this can be generalized as follows. n 8 12 16 20 24 28 32 48 2 n = f o m ? f c number of points = 2 n 256 4,096 65,536 1,048,576 16,777,216 268,435,456 4,294,967,296 281,474,976,710,656 m = jump size figure 3: digital phase wheel for an n-bit phase accumulator (n generally ranges from 24 to 32 in most dds systems), there are 2 n possible phase points. the digital word in the delta phase register, m, represents the amount the phase accumulator is incremented each clock cycle. if f c is the clock frequency, then the frequency of the output sinewave is equal to: . 2 fm f n c o ? = eq. 1 this equation is known as the dds "tuning equation." note that the frequency resolution of the system is equal to f c /2 n . for n = 32, the resolution is greater than one part in four billion! in a practical dds system, all the bits out of the phase accumulator are not passed on to the lookup table, but are truncated, leaving only the first 13 to 15 msbs. this reduces the size of the lookup table and does not affect the frequency resoluti on. the phase truncation only adds a small but acceptable amount of phase noise to the final output. (see figure 4). page 3 of 9
MT-085 normalized frequency - f out / f clk 0 -20 -40 -60 -80 -100 -120 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 figure 4: calculated output spectrum shows 90 db sfdr for 15-bit phase truncation the resolution of the dac is typically 2 to 4 bits less than the width of the lookup table. even a perfect n-bit dac will add quantization noise to the output. figure 4 shows the calculated output spectrum for a 32-bit phase accumulator, 15-bit phase truncation. the value of m was chosen so that the output frequency was sligh tly offset from 0.25 times the clock frequency. note that the spurs caused by the phase truncation and th e finite dac resolution are all at least 90 db below the fullscale output. this performance far exceeds that of any commercially available 12- bit dac and is adequate for most applications. the basic dds system described above is ex tremely flexible and has high resolution. the frequency can be changed instantaneously with no phase discontinuity by simply changing the contents of the m-register. however, practical dds systems first require the execution of a serial, or byte-loading sequence to get the new frequency word into an internal buffer register which precedes the parallel-output m-register. th is is done to minimize package pin count. after the new word is loaded into the buffer register, th e parallel-output delta phas e register is clocked, thereby changing all the bits simultaneously. the nu mber of clock cycles required to load the delta-phase buffer register determines the maxi mum rate at which the output frequency can be changed. aliasing in dds systems there is one important limitation to the range of output frequencies that can be generated from the simple dds system. the nyquist criteria stat es that the clock frequency (sample rate) must be at least twice the output fr equency. practical limitations rest rict the actual highest output frequency to about 1/3 the clock frequency. figure 5 shows the output of a dac in a dds page 4 of 9
MT-085 system where the output frequency is 30 mhz and the clock frequency is 100 mhz. an antialiasing filter must follow the reconst ruction dac to remove the lower image frequency (100 30 = 7 figure 5: aliasing in a dds system ultiples thereof. the exact equation for the normalized output amplitude, a(f o ), is given by: here f is the output frequency and f is the clock frequency. nse is relatively flat up to e maximum output dac frequency (generally 1/3 the update rate). ? 0 mhz) as shown in the figure. f c 100mhz db note that the amplitude response of the dac output (before filtering) follows a sin(x)/x response with zeros at the clock frequency and m w o c this rolloff is because the dac out put is not a series of zero-widt h impulses (as in a perfect re- sampler), but a series of recta ngular pulses whose width is equal to the reciprocal of the update rate. the amplitude of the sin(x)/x response is down 3.92 db at the nyquist frequency (1/2 the dac update rate). in practice, th e transfer function of the antialiasing filter can be designed to compensate for the sin(x)/x rolloff so that the over all frequency respo th another important consideration is that, unlike a pll-based system, the higher order harmonics of the fundamental output frequency in a dds sy stem will fold back into the baseband because of aliasing. these harmonics cannot be removed by the antialiasing filter . for instance, if the clock frequency is 100 mhz, and the output frequency is 30 mhz, the second harmonic of the af o f o f c f o () sin = ? ? ? ? ? ? f c eq. 2 frequency (mhz) lpf image image f c 2 0 10 20 30 40 50 60 70 80 90 100 110 120 130 f o 30mhz 3 3 3 4 4 4 2 2 3.92 db (nyquist) 0 c o c o o f f f f sin )f(a ? ? ? ? ? ? ? ? = f c 100mhz db frequency (mhz) lpf image image f c 2 0 10 20 30 40 50 60 70 80 90 100 110 120 130 f o 30mhz 3 3 3 4 4 4 2 2 (nyquist) 0 c o c o o f f f f sin )f(a ? ? ? ? ? ? ? ? = 3.92 db page 5 of 9
MT-085 30 mhz output signal appears at 60 mhz (out of band), but also at 100 ? 60 = 40 mhz (the aliased component. similarly, the third harmonic (90 mhz) appears in band at 100 ? 90 = 10 mhz, and the fourth at 120 ? 100 mhz = 20 mhz. higher order harmonics also fall within the yquist bandwidth (dc to f c /2). the location of the first four harmonics is shown in the figure. ds systems as adc clock drivers n d dds systems such as the ad9850 provide an excellent method of generating the sampling clock to the adc, especially when the adc sampling frequency must be under software control and locked to the system clock (see figure 6). the true dac output current i out , drives a 200 , 42 mhz lowpass filter which is source and load te rminated, thereby making the equivalent load 100 . the filter removes spurious frequency component s above 42 mhz. the filt ered output drives one input of the ad9850 in ternal comparator. the complementary dac output current drives a 100 load. the output of the 100 k resistor divider placed between the two outputs is ecoupled and generates the reference vo ltage for the internal comparator. ut edges is le ss than 20 ps rms. true and omplementary outputs are available if required. figure 6: using a dds syst em as an adc clock drivers s, nd the resulting degradation in snr must be considered in wide dynamic range applications . mplitude modulation in a dds system d the comparator output has a 2 ns rise a nd fall time and generates a ttl/cmos-compatible square wave. the jitter of the comparator outp c dac output 125 mhz cmos adc clock drivers freq. control ad9850 dds/dac synthesizer i i 200 100k 42mhz 200 lpf 100k 470pf 100 - + 200 in the circuit shown (figure 6), the total output rms jitter for a 40 msps adc clock is 50 ps rm a a amplitude modulation in a dds system can be accomplished by placing a digital multiplier between the lookup table and the dac input as shown in figure 7. another method to modulate page 6 of 9
MT-085 the dac output amplitude is to vary the refere nce voltage to the dac. in the case of the ad9850, the bandwidth of the internal reference c ontrol amplifier is approximately 1 mhz. this me signal does he spectral purity of the dac output is of primary concern. nfortunately, the measurement, prediction, and anal ysis of this pe rformance is complicated by a s highly signal dependent. if the output frequency is slightly offset, however, the uantization noise will become more random, th ereby giving an improvement in the effective thod is useful for relatively small output amp litude changes as long as the output not exceed the +1 v compliance specification. f c phase accumulator n sin lookup table dac am register n multiplier output v ref figure 7: amplitude modulation in a dds system spurious free dynamic range cons iderations in dds systems in many dds applications, t u number of interacting factors. even an ideal n-bit dac will produce harmonics in a dds system. the amplitude of these harmonics is highly dependent upon the ratio of the output frequency to th e clock frequency. this is because the spectral c ontent of the dac quanti zation noise varies as this ratio varies, even though its theoretical rms value remains equal to q/ 12 (where q is the weight of the lsb). the assumption that the quantizat ion noise appears as white noise and is spread uniformly over the nyquist bandwidth is simply not true in a dds system (it is more apt to be a true assumption in an adc-based system, because the adc adds a certain amount of noise to the signal which tends to "dither" or randomize the quantization error. however, a certain amount of correlation still exists). for instance, if the dac output freque ncy is set to an exact submultiple of the clock frequency, then the quantization noise will be con centrated at multiples of the output frequency, i.e., it i q sfdr. this is illustrated in figure 8, where a 4096 (4k) point fft is calculated based on digitally generated data from an ideal 12-bit dac. in th e left-hand diagram (a), the ratio between the clock frequency and the output frequency was c hosen to be exactly 40, yielding an sfdr of page 7 of 9
MT-085 about 77 ow incr ightly c digital noise is set to bout 1 the h flexibility sele dbc. in the right-hand diagram, the ratio was slightly offset, and the effective sfdr is eased to 94 dbc. in this ideal case, we observed a change in sfd r of 17 db just by hanging the frequency ratio. n sl (a) f out = 2.0000 mhz, f s = 80.0000 mhz (b) f out = 2.0111 mhz, f s = 80.0000 mhz fft size = 8192 sfdr = 77dbc sfdr = 94dbc theoretical 12-bit snr = 74db fft process gain = 36db fft noise floor = 110dbfs figure 8: effect of ratio of clo ck to output frequency on theoretical 12-bit dac sfdr using 4096-point fft best sfdr can therefore be obtained by the careful selection of the clock and output frequencies. however, in some applications, th is may not be possible. in adc-based systems, adding a small amount of random no ise to the input tends to ra ndomize the quantiz ation errors and reduce this effect. the same thing can be d one in a dds system as shown in figure 9 (see references 8, 9, 10). the pseudo-ra ndom digital noise generator out put is added to the dds sine amplitude word before being loaded into the dac . the amplitude of the a /2 lsb. this accomplishes the randomization process at the expense of a slight increase overall output noise floor. in most dds a pplications, however, there is enoug cting the various frequency ratios so that dithering is not required. in in f c dac m v n = rms pseudorandom number phase accumu- lator delta phase register sine lookup table adder q 2 generator figure 9: injection of digital dither in a dds system to randomize quantization noise and increase sfdr page 8 of 9
page 9 of 9 MT-085 the analog device's on-line design tool, adisimdds , is an interactive tool to assist the user in selecting and evaluating dds ics. it allows th e user to select a de vice, enter the desired operating conditions, and evaluate its general performanc e. the tool uses mathematical equations approximate the overall performance of the selected device and does not calculate all possible he tool should be used as a design aid only and is not intended to be used as a placement for actual hardware testing and evaluation. es: to errors. therefore, t re re refe nc 1. ask the application engineer?33: all about direct digital synthesis ( analog dialogue , vol. 38 , a ugust 30, no. 3 20 04). 2. "single-chip direct digital synthesis vs. the analog pll," ( analog dialogue , vol. , 1996. 3. dds design , by david brandon, edn , may 13, 2004. 4. a technical tutorial on digital signal synthesis, 1999, analog devices, inc. . 5 direct digital synthesis frequently asked questions , analog devices, inc. 6. david buchanan, "choosing dacs for direct digital synthesis," application note an-237 , analog devices, inc. 7. david brandon, "direct digital synthesizers in clocking applications," application note an-823 , analog devices, 2006. 8. richard j. kerr and lindsay a. weaver, "pseudorandom dither for frequency synthesis noise," u.s. patent 4,901,265 , filed december 14, 1987, issued february 13, 1990. 9. h enry t. nicholas, iii and henry samueli, "an anal ysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation," ieee 41st annual frequency control symposium digest of papers , 1987, pp. 495-502, ieee publi cation no. ch2427-3/87/0000-495. he optimization of direct digital frequency synthesizer length effects, " ieee 42nd annual frequency control symposium digest of papers ," 1988, pp. 357-363, ieee publi cation no. ch2588- 2/88/0000-357. 10. henry t. nicholas, iii and henry samueli, "t performance in the presence of finite word 11. adisimdds design tool from analog devices. 12. hank zumbahlen, basic linear design , analog devices, 2006, isbn: 0-915550-28-1. also available as linear circuit design handbook , elsevier-newnes, 2008, isbn-10: 0750687037, isbn-13: 978- 0750687034. chapter 4. 13. walt kester, analog-digital conversion , analog devices, 2004, isbn 0-916550-27-3, chapter 6. also available as the data conversion handbook , elsevier/newnes, 2005, isbn 0-7506-7841-0, chapter 6. copyright 2009, analog devices, inc. all rights reserved. analog devices assumes no responsibility for customer product design or the use or application of custom ers? products or for any infringements of patents or rights of others which may result from analog devices assistance. all trad emarks and logos are property of their respective holders. information furnished by analog devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog devices regarding technical accuracy and topicality of the content provided in analog devices tutorials.
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